Design of 32 Bit Low Power and High Speed Square Root Carry Select Adder

Author Details

K.Poornima1, B.Githendra2, S. Karthigashree3, K.Stalin4, S.Vignesh5

1Assistant Professor, 2,3,4,5UG Students – Final Year, Department of Electronics and Communication Engineering, Nandha College of Technology, Perundurai, Tamilnadu, India


In this paper, the specifications to be considered while designing any integrated circuits including adder circuit are power, speed and area. Now a days even a small device require a basic needs, which should be highly efficient and low power, so here we came up with  the flip flop. Without the use of adders and multipliers, the arithmetic operation in the digital system became incomplete. As we know that the Carry Select Adder (CSLA) is one of the fastest adder which performs the Arithmetic functions rapidly, it is clear that there is scope for reducing the area and power consumption in CSLA and one of the special case of CSLA is Square root carry select adder (SCSLA). Since SCSLA operates at high speed and reduce the power dissipation. In order to reduce both the power and area, the proposed technique of  Adaptive voltage level at source (AVLS) with True Single Phase Clocking (TSPC) based D flip flop is used instead of using Ripple Carry Adder (RCA) and Binary to Excess converter(BEC). This can make less number of transistor counts with significant power and area. In this paper, a 32 bit square root carry select adder is implemented using AVLS-TSPC based D flip-flop.

Keywords: Carry select adder (CSLA), Square root carry select adder (SCSLA), D Flip-flop, Low power, High speed, True single phase clocking(TSPC).








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