Design of Serial and Mixed Mode Flip Flop Scan Test with High Performance

Author Details

1T.Raja, 2M.Nisha, 3R.Sangeetha, 4M.Sowndarya,5G.Sri Loga

1Assistant Professor, 2,3,4,5UG Students – Final Year, Department of Electronics and Communication Engineering, Vivekanandha College of Technology for Women, Namakkal, Tamilnadu, India



The capacity of sequential sweep configuration has been the standard technique for assessing VLSI (Very Large-Scale Integration Circuits) before. Sequential output plan has turned into the non-self-plan for testability techniques over the strategy. Since it is easy to develop, the sequential sweep configuration has ruled the test design. In sequential output plan, the current sweep cell stays away from the weaknesses of earlier output cells, for example, the defer brought about by the output multiplexers connected to each flip-inputs. Flop the sequential output design, then again, produces inordinate exchanging action during testing, bringing about superfluously high power dispersal. The current sweep cell configuration is utilized as a typical output flip-flop in the “blended check” test, which permits it to work as both a sequential and a Random Access Scan (RAS) cell. In this technique, another blended mode filter plan design is suggested that consolidates sequential and arbitrary activities in a solitary module, bringing about changes in RAS cells where sequential information correspondence is inside associated with check cells in series, permitting information to be gotten in both sequential and irregular strategies from each output cell. When contrasted with the present blended mode check plan, it further develops exchanging movement and diminishes power utilization. The exploratory outcomes show that general region, power utilization, and inactivity may be in every way diminished.