Design of Serial and Mixed Mode Flip Flop Scan Test with High Performance

Author Details 1T.Raja, 2M.Nisha, 3R.Sangeetha, 4M.Sowndarya,5G.Sri Loga 1Assistant Professor, 2,3,4,5UG Students – Final Year, Department of Electronics and Communication Engineering, Vivekanandha College of Technology for Women, Namakkal, Tamilnadu, India   Abstract The capacity of sequential sweep configuration has been the standard technique for assessing VLSI (Very Large-Scale Integration Circuits) before. Sequential output plan has turned […]